1. Field of the Invention
The present invention relates to semiconductor integrated circuits and techniques for detecting physical defects and faults therein. More particularly, the present invention relates to switchable pull-up and pull-down circuits which permit accurate IDDQ defect and fault detection measurement of integrated circuits having signal lines with pull-ups and/or pull-downs and any other static current dissipating logic.
2. Description of the Related Art
Integrated circuits typically incorporate a very high density of circuit components, most of which are susceptible to a variety of different faults and physical defects. Many of the internal faults which arise during integrated circuit manufacture can be detected using various available test techniques. Testing should provide a desired level of fault and defect coverage defined in terms of a percentage of faults which are detectable in a given circuit using a particular test technique. In many integrated circuits, a fault coverage of 90% or higher is required.
One technique commonly used to detect Complementary Metal Oxide Semiconductor (CMOS) integrated circuit faults is a technique known in the art as IDDQ testing. IDDQ testing involves a precision measurement of quiescent V.sub.DD supply current under various combinations of input logic states. These combinations are known as test vectors.
IDDQ testing is based upon the fact that absent any internal faults, the quiescent V.sub.DD supply current in a typical CMOS integrated circuit should be on the order of less than 100 nanoamps. A physical defect such as bridging will produce a measurable increase in quiescent supply current in response to a particular test vector. IDDQ testing thus provides substantial benefits in terms of defect detection. A high level of defect coverage can be obtained with a reduced set of test vectors and minimal test time provided that the test vectors produce a high toggle coverage of internal logic nodes.
IDDQ testing permits a clear determination of the source of many common defects. In addition, IDDQ testing can be performed on circuits which cannot be adequately tested using other available techniques. Further detail regarding the benefits of IDDQ testing can be found in R. Fritzemeier et al., "Increased CMOS IC Stuck-at Fault Coverage with Reduced IDDQ Test Sets", International Test Conference, Sep. 10-12, 1990.
IDDQ testing was not practical for integrated circuits having signal lines with pull-ups or pull-down transistors/resistors with I/Os. A voltage pull-up is fairly common among integrated circuit input and output signal lines. Voltage pull-ups provide a number of advantages such as interface compatibility, improved noise immunity and a uniform predictable transition between voltage rails. It is therefore often desirable to maintain voltage pull-ups on many integrated circuit input and output signal lines.
An exemplary prior art integrated circuit input is shown in FIG. 1. The integrated circuit input 10 includes a signal line 12 which is connected through a pull-up mechanism 11 to a voltage source 16. An input signal applied to pad 13 is supplied to buffer 19 via signal line 12. From buffer 19 the input signal can then be applied to other parts of the integrated circuit.
Prior art integrated circuit pull-up mechanism 11 typically consists of a PMOS FET 14 with its gate connected to ground potential 18 as shown. FET 14 occupies minimal space and is therefore a preferred pull-up mechanism in size-constrained integrated circuit applications. Similar pull-up mechanisms are presently used on other integrated circuit signal lines. In circuits not subject to stringent size constraints, pull-up mechanism 11 will typically consist of a pull-up resistor. Similarly, a pull-down mechanism can be used based on NMOS.
When an IDDQ test is performed on exemplary integrated circuit input I/O, the quiescent current measurement may be masked as a result of the current flowing through pull-up mechanism 11. Since IDDQ testing depends upon the measurement of quiescent current levels on the order of about 100 microamps or less, a single voltage pull-up can interfere with the measurement.
A voltage pull-up such as that shown in FIG. 1 will generally produce a few microamps of current when a low level signal is applied to signal line 12, approximately the same amount of current increase that the IDDQ test must be able to measure on the entire integrated circuit to accurately detect certain faults and physical defects. The current masking problem is compounded in the case of Application Specific Integrated Circuits (ASICs) which may include hundreds of signal lines with pull-ups or pull-downs.
IDDQ testing can therefore not be performed accurately on integrated circuits such as ASICs which contain significant numbers of pull-ups. As a result, designers must either avoid IDDQ testing or avoid using pull-ups or pull-downs in the circuit.
Alternatives to IDDQ fault detection testing present additional problems in many applications. A popularly used technique known as logic response stuck-at fault (SAF) testing involves applying stimuli to the inputs of a particular circuit, and examining the circuit outputs to determine if a particular internal fault exists.
However, it is difficult and costly to generate a sufficient number of input signal test vectors to detect a desired level of internal faults. In circuits with inherently low controllability, a large number of internal faults may be undetectable at the output regardless of the particular stimuli applied to the inputs. Circuits of this type include random logic control circuits and asynchronous designs. A desired fault coverage therefore may not be obtained for these circuits.
Secondly, any physical defects such as bridging, gate oxide shorts, and spot defects do not map into SAF. These defects cause indeterminate logic levels at the defect site, and thus these defects cannot be detected by any logic testing method.
An alternative to functional testing involves the use of a technique known as scan design. In this technique, additional test structures are incorporated into the integrated circuit in order to facilitate testing. Software programs generate test inputs which utilize these test structures to assist in fault detection.
One example of scan design implementation is disclosed in U.S. Pat. No. 5,032,783, issued to Hwang et al. However, the added scan structures consume scarce circuit space and power, and depending upon their placement in the circuit may introduce timing problems. As a result, an integrated circuit typically must be designed from the outset to incorporate acceptable scan structures. Scan structures cannot be easily incorporated into an existing integrated circuit design. Also, stuck-at faults, and physical defects such as bridging, gate oxide defects, and spot defects, cannot be detected by scan testing.
IDDQ testing overcomes many of the difficulties of the above alternative techniques in that it can provide a relatively high fault and defect coverage of greater than 90% without an excessively large set of test vectors or requiring that additional test structures be designed into the circuit itself. However, as previously mentioned, IDDQ test techniques are not readily compatible with pull-ups, pull-downs or any other static current dissipating logic such as phase-locked loops (PLL), memory sense amplifiers, differential logic, etc.
It is therefore not possible under current practice to obtain the full benefits of accurate IDDQ testing in integrated circuits incorporating pull-ups, or other static current dissipating logic such as PLL, memory sense amplifiers, differential logic, etc. Total IDDQ current is typically minimized under presently available techniques by setting signal lines with pull-ups to a high logic level and pull-downs to a low logic level. See R. Perry, "IDDQ Testing in CMOS Digital ASICS", 1992 IEEE International Test Conference, at p. 156. Signal lines with pull-ups and pull-downs are thus classified as "don't care faults" and effectively removed from the test vector set. See R. Fritzemeier et al., at p. 4. The result is reduced IDDQ test accuracy and lower fault and defect coverage.
As is apparent from the above, there presently is a dire need for an apparatus or method capable of providing accurate IDDQ testing while simultaneously maintaining the substantial benefits associated with integrated circuit pull-ups and pull-downs. A need currently exists for a technique capable of interfacing with IDDQ test equipment such that fault coverage is improved, while not interfering with functional operation of the integrated circuit. Further, a need exists for a simple and inexpensive method and apparatus that requires only relatively minor modification of the integrated circuit pull-up and pull-down mechanism.